SI53307 Datasheet, PDF (24/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
3. Pin Description: 16-Pin QFN
V_{DD 1}
CLK1 ²
CLK1 3
GND ⁴
GND
PAD
12 Q0
11 _Q0
10 _Q1
9 _Q1
Table 20. Pin Description
Pin
Name
Description
1
VDD
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible.
2
CLK1
Input clock.
3
CLK1
Input clock (complement).
When the CLK is driven by a single-ended input, connect /CLK to VDD/2.
See Figure 1, “Differential Measurement Method Using a Balun,” on page 10.
4
GND
Ground.
5
VDDO
Output clock supply voltage.
6
CLK0
Input clock.
7
CLK0
Input clock (complement).
When the CLK is driven by a single-ended input, connect /CLK to VDD/2.
See Figure 1, “Differential Measurement Method Using a Balun,” on page 10.
8
SFOUT1
Output signal format control pin 1.
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or VDD.
24
Rev. 1.0