SI53307 Datasheet, PDF (17/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
2.8. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs can be left floating. Do not
short unused outputs to ground.
VDDO
DC-coupled LVPECL Termination Scheme 1
R1
R1
VDDO _{= 3.3 V or 2.5 V}
Si533xx
Q
50
Qn
50
3.3 V LVPECL: R1 = 127 , R2 = 82.5 
2.5 V LVPECL: R1 = 250 , R2 = 62.5 
R2
R2
VDD = VDDO
LVPECL
Receiver
VTERM = VDDO – 2 V
R1 // R2 = 50 
DC-coupled LVPECL Termination Scheme 2
VDDO _{= 3.3 V or 2.5 V}
Si533xx
Q
50
Qn
50
50
VDD = VDDO
LVPECL
Receiver
50
VTERM = VDDO – 2 V
VDD
AC-coupled LVPECL Termination Scheme 1
VDD _{= 3.3 V or 2.5 V}
Si533xx
Q
Qn
Rb Rb
R1
0.1 uF
50
50
0.1 uF
R2
R1
VDD _{= 3.3 V or 2.5 V}
LVPECL
Receiver
R2
VBIAS = VDD – 1.3 V
R1 // R2 = 50 
3.3 V LVPECL: R1 = 82.5 , R2 = 127 , Rb = 120 
2.5 V LVPECL: R1 = 62.5 , R2 = 250 , Rb = 90 
AC-coupled LVPECL Termination Scheme 2
VDDO = 3.3 V or 2.5 V
Si533xx
Q
Qn
Rb Rb
0.1 uF
50
50
0.1 uF
50
VDD _{= 3.3 V or 2.5 V}
LVPECL
Receiver
50
VBIAS = VDD – 1.3 V
3.3 V LVPECL: Rb = 120 
2.5 V LVPECL: Rb = 90 
Figure 7. LVPECL Output Termination
Rev. 1.0
17