SI53307 Datasheet, PDF (25/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Pin
9
10
11
12
13
14
15
16
GND
Pad
Si53307
Name
Q1
Q1
Q0
Q0
SFOUT0
CLK_SEL
GND
OE
GND
Table 20. Pin Description (Continued)
Output clock 1 (complement).
Description
Output clock 1.
Output clock 0 (complement).
Output clock 0.
Output signal format control pin 0.
Three-level input control. Internally biased at VDD/2. Can be left floating or tied to
ground or VDD.
Mux input select pin:
Clock inputs are switched without the introduction of glitches.
When CLK_SEL is high, CLK1 is selected.
When CLK_SEL is low, CLK0 is selected.
CLK_SEL contains an internal pull-down resistor.
Ground.
Output enable.
When OE = high, all outputs are enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE contains an internal pull-up resistor.
Ground.
Rev. 1.0
25