SI53307 Datasheet, PDF (21/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
2.10. Typical Phase Noise Performance
Each of the following three figures shows three phase noise plots superimposed on the same diagram.
Source Jitter: Reference clock phase noise.
Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz.
Total Jitter (Diff'l): Combined source and clock buffer phase noise measured as a differential output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is
made using a balun. See Figure 1 on page 10.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer
can then be calculated (via root-sum-square addition).
Total Jitter (SE) = 147.8fs
Additive Jitter (SE) = 142.8fs
Total Jitter (Diff) = 118fs
Additive Jitter (Diff) = 112fs
Source Jitter = 38.2fs
Diff’l Input
Frequency Slew Rate
(MHz)
(V/ns)
Source
Jitter
(fs)
Total Jitter
(SE)
(fs)
Additive Jitter
(SE)
(fs)
Total Jitter (Diff)
(fs)
156.25
1.0
38
14
14
118
Figure 11. Source, Additive, and Total Jitter (156.25 MHz)
Additive
Jitter (Diff)
(fs)
112
Rev. 1.0
21