SI53307 Datasheet, PDF(5/30 Page) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

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SI53307 Datasheet, PDF (5/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

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Si53307

Table 3. DC Common Characteristics

(VDD = VDDO = 1.8 V ï±ï 5%, 2.5 V ï± 5%, or 3.3 V ï±ï 10%,TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply Current

IDD

100

Output Buffer

IDDO

LVPECL (3.3 V)

Supply Current

(Per Clock Output)

Low Power LVPECL (3.3 V)*

@100 MHz (diff)

LVDS (3.3 V)

@200 MHz (CMOS)

CML (3.3 V)

HCSL, 100 MHz, 2 pF load

(3.3 V)

CMOS (2.5 V, SFOUT = Open/0),

per output, CL = 5 pF, 200 MHz

CMOS (3.3 V, SFOUT = 0/1),

per output, CL = 5 pF, 200 MHz

Input High Voltage

VIH

SFOUTX, OE

0.8 x VDD

Input Mid Voltage

VIM

SFOUTX, 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD V

Input Low Voltage

VIL

SFOUTX, OE

0.2 x VDD V

Internal Pull-down

Resistor

RDOWN

SFOUT, CLK_SEL

kï

Internal Pull-up

RUP

Resistor

SFOUTX, OE

kï

*Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.

Rev. 1.0

▷