SI53307 Datasheet, PDF (13/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
VDDO
DC-coupled LVPECL Termination Scheme 1
VDDO_{= 3.3 V or 2.5 V}
R1
R1
“Standard”
50
LVPECL
Driver
50
CLKx
/CLKx
VDD
Si533xx
3.3 V LVPECL: R1 = 127 , R2 = 82.5 
2.5 V LVPECL: R1 = 250 , R2 = 62.5 
R2
R2
VTERM = VDDO – 2 V
R1 // R2 = 50 
DC-coupled LVPECL Termination Scheme 2
VDDO _{= 3.3 V or 2.5 V}
“Standard”
50
LVPECL
Driver
50
50
50
CLKx
/CLKx
VDD
Si533xx
VTERM = VDDO – 2 V
DC-coupled LVDS Termination
VDDO = 3.3 V or 2.5 V
Standard
50
LVDS
Driver
50
CLKx
/CLKx
100
VDD
Si533xx
DC-coupled HCSL Source Termination Scheme
VDDO _{= 3.3 V}
33
Standard
HCSL Driver
33
50
CLKx
/CLKx
50
VDD
Si533xx
50
50
Note: 33  series termination is optional depending on the location of the receiver.
DC-coupled HCSL Receiver Termination Scheme
VDDO = 3.3 V
Standard
Q
50
HCSL
Qn
Driver
50
VDD ^Si533xx
50 
50 
Figure 4. Differential DC-coupled Input Terminations
Rev. 1.0
13