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SI53307 Datasheet, PDF (4/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |||
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Si53307
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min
Typ
Max Unit
â40
â
85
°C
1.71
1.8
1.89 V
2.38
2.5
2.63 V
2.97
3.3
3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97
3.3
3.63 V
HCSL
2.97
3.3
3.63 V
Output Buffer Supply
Voltage*
VDDO
LVDS, CML, LVCMOS
1.71
1.8
1.89 V
2.38
2.5
2.63 V
2.97
3.3
3.63 V
LVPECL, low power LVPECL
2.38
2.5
2.63 V
2.97
3.3
3.63 V
HCSL
2.97
3.3
3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent.
Table 2. Input Clock Specifications
(VDD=1.8 V ï± 5%, 2.5 V ï± 5%, or 3.3 V ï± 10%, TA=â40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Differential Input Common VCM
Mode Voltage
VDD = 2.5 Vï± 5%, 3.3 Vï± 10%
0.05
â
â
V
Differential Input Swing
VIN
(peak-to-peak)
0.2
â
2.2
V
LVCMOS Input High Volt-
VIH
VDD = 2.5 Vï± 5%, 3.3 Vï± 10% VDD x 0.7
â
age
â
V
LVCMOS Input Low Volt-
VIL
VDD = 2.5 Vï± 5%, 3.3 Vï± 10%
â
age
â
VDD x V
0.3
Input Capacitance
CIN
CLK pins with respect to GND
â
5
â
pF
4
Rev. 1.0
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