SI53307 Datasheet, PDF (23/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
Source Jitter = 23.4fs
Total Jitter (SE) = 5fs
Additive Jitter (SE) = 5fs
Total Jitter (Diff) = 5fs
Additive Jitter (Diff) = 5fs
Diff Input
Frequency Slew Rate
(MHz)
(V/ns)
Source
Jitter
(fs)
Total Jitter
(SE)
(fs)
Additive Jitter
(SE)
(fs)
Total Jitter (Diff)
(fs)
625
1.0
23
5
5
5
Figure 13. Source, Additive, and Total Jitter (625 MHz)
Additive
Jitter (Diff)
(fs)
5
2.11. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs, and
SoCs and may reduce board-level filtering requirements. For more information, see application note, “AN491:
Power Supply Rejection for Low Jitter Clocks”.
Rev. 1.0
23