SI53307 Datasheet, PDF (1/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR
Features
 2 differential or 4 LVCMOS outputs  2:1 input mux with glitchless input
 Ultra-low additive jitter: 45 fs rms
clock switching
 Wide frequency range: 1 to 725 MHz ^{ Independent V}_DD ^{and V}_DDO ^:
 Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, low power  Small size: 16-QFN (3 mm x 3 mm)
LVPECL, LVDS, CML, HCSL,
 RoHS compliant, Pb-free
LVCMOS
 Synchronous output enable
 Industrial temperature range:
–40 to +85 °C
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53307 is an ultra-low jitter two output differential buffer with pin-selectable
output clock signal format and 2:1 input clock mux. The Si53307 utilizes Silicon
Labs' advanced CMOS technology to fanout clocks from 1 to 725 MHz with
guaranteed low additive jitter, low skew, and low propagation delay variability. The
Si53307 features minimal cross-talk and provides superior supply noise rejection,
simplifying low jitter clock distribution in noisy environments. Independent core
and output bank supply pins provide integrated level translation without the need
for external circuitry.
Functional Block Diagram
Ordering Information:
See page 26.
Pin Assignments
V_{DD 1}
CLK1 2
CLK1 3
GND 4
GND
PAD
12 Q0
11 Q0
10 _Q1
9 _Q1
Patents pending
Rev. 1.0 11/14
Copyright © 2014 by Silicon Laboratories
Si53307