SI53307 Datasheet, PDF (10/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
Table 12. Additive Jitter, Single-Ended Clock Input
V_DD
Input^1,2
Output
Freq
(MHz)
Clock Format
Amplitude
V_IN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
3.3
200 Single-ended
1.70
1
LVCMOS⁴
3.3 156.25 Single-ended
2.18
1
LVPECL
3.3 156.25 Single-ended
2.18
1
LVDS
3.3 156.25 Single-ended
2.18
1
LVCMOS⁴
2.5
200 Single-ended
1.70
1
LVCMOS⁵
2.5 156.25 Single-ended
2.18
1
LVPECL
2.5 156.25 Single-ended
2.18
1
LVDS
2.5 156.25 Single-ended
2.18
1
LVCMOS⁵
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Typ
Max
120
160
160
185
150
200
130
180
120
160
145
185
145
195
140
180
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input (see Figure 1).
LVCMOS jitter is measured single-ended.
4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11).
5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11).
CLK SYNTH
SMA103A
PSPL 5310A
Balun
CLKx
Si533xx
50
DUT
50
/CLKx
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50ohm
Figure 1. Differential Measurement Method Using a Balun
10
Rev. 1.0