SI53307 Datasheet, PDF (8/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
Table 10. AC Characteristics (Continued)
(V_DD = V_DDO = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Output Rise/Fall Time
Symbol
Test Condition
Min
T_R/T_F LVPECL, LVDS, CML, HCSL¹, Low- —
Power LVPECL 20/80%
Typ Max Unit
—
350
ps
200 MHz, 20/80%,
2 pF load (LVCMOS), 12 mA
—
—
750
ps
Minimum Input Pulse
T_W
Width
500
—
—
ps
Additive Jitter
J
V_DD = V_DDO = 2.5/3.3 V, LVPECL/
—
50
65
fs
(Differential Clock Input)
LVDS, F = 725 MHz, 0.75 V/ns
input slew rate
Propagation Delay
Output Enable Time
T_PLH,
T_PHL
T_EN
LVPECL
LVDS
F = 1 MHz
F = 100 MHz
675
875 1075
ps
675
875 1075
ps
—
1500
—
ns
—
20
—
ns
F = 725 MHz
—
5
—
ns
Output Disable Time
T_DIS
Output to Output Skew²
T_SK
F = 1 MHz
F = 100 MHz
F = 725 MHz
LVCMOS, drive 12 mA to 2 pF
LVPECL
—
2000
—
ns
—
35
—
ns
—
5
—
ns
—
50
120
ps
—
30
75
ps
Part to Part Skew³
Power Supply Noise
Rejection⁴
T_PS
PSRR
LVDS
Differential
10 kHz sinusoidal noise
100 kHz sinusoidal noise
—
40
85
ps
—
—
150
ps
—
–72.5
—
dBc
—
–70
—
dBc
500 kHz sinusoidal noise
—
–67.5
—
dBc
1 MHz sinusoidal noise
—
–62.5
—
dBc
Notes:
1. HCSL measurements were made with receiver termination. See Figure 8 on page 18.
2. Output to Output skew specified for outputs with an identical configuration.
3. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDO (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See application note, “AN491: Power Supply Rejection for Low Jitter Clocks” for further details.
8
Rev. 1.0