SI53307 Datasheet, PDF (7/30 Pages) Silicon Laboratories – 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Si53307
Table 8. Output Characteristics—LVCMOS
(V_DD = V_DDO = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Output Voltage High^* V_OH
0.75 x V_DDO
—
—
Output Voltage Low^*
V_OL
—
—
0.25 x V_DDO
*Note: I_OH and I_OL per the Output Signal Format Table for specific V_DDO and SFOUTX settings.
Unit
V
V
Table 9. Output Characteristics—HCSL
(V_DD = V_DDO = 3.3 V ± 10%, TA = –40 to 85 °C)
Parameter
Output Voltage High
Output Voltage Low
Single-Ended
Output Swing
Crossing Voltage
Symbol
V_OH
V_OL
V_SE
V_C
Test Condition
R_L = 50  to GND
R_L = 50  to GND
R_L = 50  to GND
R_L = 50  to GND
Min
Typ
Max
Unit
550
700
850
mV
–150
0
150
mV
550
700
850
mV
250
350
550
mV
Table 10. AC Characteristics
(V_DD = V_DDO = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Frequency
Symbol
Test Condition
Min
F LVPECL, low power LVPECL, LVDS, 1
CML, HCSL
LVCMOS
1
Typ Max Unit
—
725 MHz
—
200 MHz
Duty Cycle
D_C
Note: 50% input duty cycle.
Minimum Input Clock
SR
Slew Rate
200 MHz, 20/80%T_R/T_F<10% of
40
50
period (LVCMOS)
(12 mA drive)
20/80% T_R/T_F<10% of period
(Differential)
48
50
Required to meet prop delay and 0.75
—
additive jitter specifications
(20–80%)
60
%
52
%
—
V/ns
Notes:
1. HCSL measurements were made with receiver termination. See Figure 8 on page 18.
2. Output to Output skew specified for outputs with an identical configuration.
3. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDO (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See application note, “AN491: Power Supply Rejection for Low Jitter Clocks” for further details.
Rev. 1.0
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