SI5324C-C-GM Datasheet, PDF (9/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Table 3. AC Characteristics
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XA_RIN RATE[1:0] = LM, ML, MH,
—
12
—
k
or HM, ac coupled
Input Voltage Swing
XA_VPP RATE[1:0] = LM, ML, MH,
0.5
—
1.2
V_PP
or HM, ac coupled
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XB_VPP RATE[1:0] = LM, ML, MH,
0.5
—
2.4
V_PP
or HM
CKINn Input Pins
Input Frequency
CKN_F
0.002
—
Input Duty Cycle
CKN_DC
Whichever is smaller
40
—
(Minimum Pulse Width)
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
2
—
710
MHz
60
%
—
ns
Input Capacitance
CKN_CIN
Input Rise/Fall Time
CKN_TRF
20–80%
See Figure 2
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not configured
for CMOS or
Disabled)
CKO_F
N1  6
N1 = 5
N1 = 4
—
—
3
pF
—
—
11
ns
0.002
—
970
—
1.213
—
945
1134
1.4
MHz
MHz
GHz
Maximum Output
Frequency in CMOS
Format
CKO_F
—
—
212.5
MHz
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
Rev. 1.0
9