SI5324C-C-GM Datasheet, PDF (25/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

5. Register Descriptions
Si5324
Register 0.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FREE_RUN
CKOUT_
ALWAYS_ON
BYPASS_
REG
Type
R
R/W
R/W
R
R
R
R/W
R
Reset value = 0001 0100
Bit
Name
Function
7
Reserved Reserved.
6 FREE_RUN Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB
reference.
0: Disable
1: Enable
5
CKOUT_ CKOUT Always On.
ALWAYS_ON _{This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on}
and ICAL is not complete or successful. See Table 11 on page 24.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output.
Notes:
1. The frequency may be significantly off until the part is calibrated.
2. Must be 1 to control output to output skew.
4:2 Reserved Reserved.
1
BYPASS_ Bypass Register.
REG
This bit enables or disables the PLL bypass mode. Use only when the device is in digital
hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
0
Reserved Reserved.
Rev. 1.0
25