SI5324C-C-GM Datasheet, PDF (18/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
3. Functional Description
Xtal or Refclock
CKIN1
CKIN2
÷ N31
÷ N32
Xtal/Refclock
DSPLL^®
÷ N2
÷N1_HS
÷ NC1_LS
÷ NC2_LS
CKOUT1
CKOUT2
Loss of Signal/
Frequency Offset
Loss of Lock
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
I²C/SPI Port
Device Interrupt
Rate Select
Clock Select
Skew Adjust
Figure 5. Si5324 Functional Block Diagram
The Si5324 is a low loop bandwidth, jitter-attenuating
clock multiplier for high performance applications. The
Si5324 accepts two input clocks ranging from 2 kHz to
710 MHz and generates two output clocks ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The Si5324 can also use its external reference as a
clock source for frequency synthesis. The device
provides virtually any frequency translation combination
across this operating range. Independent dividers are
available for each input clock and output clock, so the
Si5324 can accept input clocks at different frequencies
and it can generate output clocks at different
frequencies. The Si5324 input clock frequency and
clock multiplication ratio are programmable through an
I²C or SPI interface. Silicon Laboratories offers a PC-
based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This utility can be downloaded from
http://www.silabs.com/timing.
The Si5324 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5324
PLL loop bandwidth is digitally programmable and
supports a range from 4 Hz to 525 Hz. A fast lock
feature is available to reduce lock times inherent with
low loop bandwidth PLLs. The DSPLLsim software
utility can be used to calculate valid loop bandwidth
settings for a given input clock frequency/clock
multiplication ratio.
The Si5324 supports hitless switching between the two
synchronous input clocks in compliance with Telcordia
GR-253-CORE that greatly minimizes the propagation
of phase transients to the clock outputs during an input
clock transition (maximum 200 ps phase change).
Manual and automatic revertive and non-revertive input
clock switching options are available. The Si5324
monitors both input clocks for loss-of-signal (LOS) and
provides a LOS alarm when it detects missing pulses on
either input clock. The device monitors the lock status of
the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. Due to the
low loop bandwidth of the part, the LOL indicator clears
before the loop fully settles.
The Si5324 also monitors frequency offset alarms
(FOS), which indicate if an input clock is within a
specified frequency ppm accuracy relative to the
frequency of an XA/XB reference clock. Both Stratum
3/3E and SONET Minimum Clock (SMC) FOS
thresholds are supported.
The Si5324 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average frequency that existed a
fixed amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
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Rev. 1.0