SI5324C-C-GM Datasheet, PDF (29/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Register 6.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
SFOUT2_REG [2:0]
SFOUT1_REG [2:0]
Type
R
R
R/W
R/W
Reset value = 0010 1101
Bit
Name
Function
7:6 Reserved Reserved.
5:3 SFOUT2_ SFOUT2_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT2 output buffer. Bypass mode is not}
supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0 SFOUT1_ SFOUT1_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not}
supported for CMOS output clocks.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Rev. 1.0
29