SI5324C-C-GM Datasheet, PDF (11/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Table 3. AC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Device Skew
Min
Typ
Max
Unit
Output Clock Skew
t_SKEW
 of CKOUTn to  of
—
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
Phase Change due to
t_TEMP
Max phase changes from
—
Temperature Variation¹
–40 to +85 °C
PLL Performance
(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)
Lock Time²
t_LOCKMP Start of ICAL to of LOL
—
Settle Time²
t_SETTLE Start of ICAL to Fout within
—
5 ppm of final value
Output Clock Phase
t_{P_STEP}
After clock switch
—
Change
f3  128 kHz
Closed Loop Jitter
Peaking
Jitter Tolerance
J_PK
J_TOL
—
Jitter Frequency Loop 5000/BW
Bandwidth
Phase Noise
CKO_PN
100 Hz Offset
—
fout = 622.08 MHz
1 kHz Offset
—
—
300
0.8
4.2
200
0.05
—
–90
–106
100
ps
500
ps
1.0
s
5.0
s
—
ps
0.1
dB
—
ns pk-pk
—
dBc/Hz
—
dBc/Hz
10 kHz Offset
—
–121
—
dBc/Hz
100 kHz Offset
—
–132
—
dBc/Hz
1 MHz Offset
—
–132
—
dBc/Hz
Subharmonic Noise
SP_SUBH Phase Noise @ 100 kHz
—
–88
–76
dBc
Offset
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
–93
–70
dBc
(n  1, n x F3 < 100 MHz)
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
Rev. 1.0
11