SI5324C-C-GM Datasheet, PDF(10/72 Page) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

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SI5324C-C-GM Datasheet, PDF (10/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

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Si5324

Table 3. AC Characteristics (Continued)

(VDD = 1.8 Â± 5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Output Rise/Fall

(20â80 %) @

622.08 MHz output

CKOTRF Output not configured for

CMOS or Disabled

See Figure 2

Output Rise/Fall

(20â80%) @

212.5 MHz output

Output Rise/Fall

(20â80%) @

212.5 MHz output

Output Duty Cycle

Uncertainty @

622.08 MHz

CKOTRF

CMOS Output

VDD = 1.71

CLOAD = 5 pF

CKOTRF

CMOS Output

VDD = 2.97

CLOAD = 5 pF

CKODC

100 ï Load

Line-to-Line

Measured at 50% Point

(Not for CMOS)

LVCMOS Input Pins

Typ

Max

Unit

230

350

+/-40

Minimum Reset Pulse

Width

Reset to Microproces-

sor Access Ready

LVCMOS Output Pins

tRSTMN

tREADY

Âµs

Rise/Fall Times

tRF

CLOAD = 20pf

See Figure 2

LOSn Trigger Window LOSTRIG From last CKINn ïï to ï¯

Internal detection of LOSn

N3 â 1

4.5 x N3 TCKIN

Time to Clear LOL after

LOS Cleared

tCLRLOL

ï¯LOS to ï¯LOL

Fold = Fnew

Stable Xa/XB reference

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit

the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

to submit a technical support request regarding the lock time of your frequency plan.

Rev. 1.0

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