SI5324C-C-GM Datasheet, PDF (60/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Pin # Pin Name I/O Signal Level
Description
4
C2B
O LVCMOS CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for
CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
5, 10, 32
V_DD
V_DD
Supply Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following Vdd pins:
5
0.1 µF
10 0.1 µF
32 0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
7
XB
I
Analog External Crystal or Reference Clock.
6
XA
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by RATE[1:0] pins.
8, 31, 20,
19
GND
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
RATE0 I
3-Level External Crystal or Reference Clock Rate.
15
RATE1
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to V_DD/2.
H setting corresponds to V_DD.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
16
CKIN1+ I
17
CKIN1–
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
CKIN2+ I
13
CKIN2–
Multi
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
60
Rev. 1.0