SI5324C-C-GM Datasheet, PDF(7/72 Page) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

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SI5324C-C-GM Datasheet, PDF (7/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

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Si5324

Table 2. DC Characteristics (Continued)

(VDD = 1.8 Â± 5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Output Drive Current

(CMOS driving into

CKOVOL for output low

or CKOVOH for output

high. CKOUT+ and

CKOUTâ shorted

externally)

CKOIO

2-Level LVCMOS Input Pins

ICMOS[1:0] = 11

VDD = 1.8 V

ICMOS[1:0] = 10

VDD = 1.8 V

ICMOS[1:0] = 01

VDD = 1.8 V

ICMOS[1:0] = 00

VDD = 1.8 V

ICMOS[1:0] = 11

VDD = 3.3 V

ICMOS[1:0] = 10

VDD = 3.3 V

ICMOS[1:0] = 01

VDD = 3.3 V

ICMOS[1:0] = 00

VDD = 3.3 V

Min

Typ

7.5

5.5

3.5

1.75

Max

Unit

Input Voltage Low

VIL

VDD = 1.71 V

0.5

VDD = 2.25 V

0.7

VDD = 2.97 V

0.8

Input Voltage High

VIH

VDD = 1.89 V

1.4

VDD = 2.25 V

1.8

VDD = 3.63 V

2.5

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD â¥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

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