SI5324C-C-GM Datasheet, PDF (32/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Register 10.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
DSBL2_REG DSBL1_REG
Type
R
R
R
R
R/W
R/W
R
R
Reset value = 0000 0000
Bit
Name
Function
7:4 Reserved Reserved.
3 DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the NC2_LS output divider is also powered down.
0: CKOUT2 enabled.
1: CKOUT2 disabled.
2 DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the NC1_LS output divider is also powered down.
0: CKOUT1 enabled.
1: CKOUT1 disabled.
1:0 Reserved Reserved.
Register 11.
Bit
D7
D6
D5
D4
D3
D2
Name
Type
R
R
R
R
R
R
Reset value = 0100 0000
Bit
Name
Function
7:2 Reserved Reserved.
1
PD_CK2 PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled.
1: CKIN2 disabled.
0
PD_CK1 PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled.
1: CKIN1 disabled.
D1
PD_CK2
R/W
D0
PD_CK1
R/W
32
Rev. 1.0