SI5324C-C-GM Datasheet, PDF (54/72 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/ JITTER ATTENUATOR

Si5324
Register 136.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name RST_REG ICAL
Type
R/W
R/W
R
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
Function
7
RST_REG Internal Reset (Same as Pin Reset).
Note: The I²C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
6
ICAL
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence.
ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-
tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)
must be present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-
bration, LOL will go low.
5:0
Reserved Reserved.
54
Rev. 1.0