K3S7V2000M-TC Datasheet, PDF (9/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as a reference for SMROM operation. A square wave signal(CLK) must be applied externally at cycle time
tCC. All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between VIL and VIH.
During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of set-up and hold time
around the positive edge of the clock for proper functionality and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock into the SMROM and is asserted high during all cycles, except for power down, stand-by and
clock suspend mode. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is sus-
pended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes low. The SMROM remains in the power down mode ignoring other inputs
for as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at
least "1 CLK + tSS" before the rising edge of the clock, then the SMROM becomes active from the same clock edge accepting all the
input commands.
NOP and DEVICE DESELECT
When RAS, CAS and MR are high, the SMROM performs no operation (NOP). NOP does not initiate any new operation. Device
deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR and all
the address inputs are ignored. In addition, entering a mode register set command in the middle of a normal operation, results in an
illegal state in SMROM.
POWER-UP
The following power-up sequence is recommended.
1. Apply power and start clock, Attempt to maintain MR, CKE and DQM inputs to pull them high and the other pins are NOP condition
at the inputs before or along with VDD(and VDDQ) supply.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 20us.
3. When user wants to change the default mode register set values, perform a MODE REGISTER SET cycle to program the RAS
latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is
used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other
power-up sequence.
MODE SELECTION CONTROL
Mode selection control is decided simultaneously with column access, and according to WORD pin voltage level. High level signifies
double word mode(x32) and low level signifies word mode(x16).
ADDRESS DECODING
The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select
pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column address.