K3S7V2000M-TC Datasheet, PDF(22/27 Page) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

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K3S7V2000M-TC Datasheet, PDF (22/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

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K3S7V2000M-TC

Technical Notes (Continuous)

2. CAS Interrupt

Read interrupted by Read (BL=4)Note 1

CLK

CMD

RD RD

ADD

Data(CL2)

QB0 QB1 QB2 QB3

Data(CL3)

QB0 QB1 QB2 QB3

Data(CL4)

QB0 QB1 QB2 QB3

Note 2

*Note :

1. By " Interrupt", It is meant to stop burst read by external command before the end of burst.

By "CAS Interrupt", to stop burst read by CAS access.

2. CAS to CAS delay. (=1CLK)

Synch. MROM

3. Read interrupt operation by issuing the precharge or Burst Stop Command

CASE I ) Issued read Interrupt command during burst read operation period.

CLK

CMD

Data(CL2)

Data(CL3)

Data(CL4)

PRE

Note 1

Q0 Q1

CLK

CMD

Data(CL2)

Data(CL3)

Data(CL4)

CASE II ) Issued read Interrupt command between read command and data out.

STOP

Note 1

Q0 Q1

CLK

CMD

Data(CL2)

Data(CL3)

Data(CL4)

RD PRE

Note 2

CLK

CMD

Data(CL2)

Data(CL3)

Data(CL4)

RD STOP

Note 2

*Note :

1. The data bus goes to High-Z after CAS Latency from the burst stop (or precharge) command.

2. Valid output data will last up to CL-1 clock cycle from PRE command.

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