K3S7V2000M-TC Datasheet, PDF (25/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
5. Read cycle depending on tVCVC
@ RL = 2, CL = 5, BL = 4 ; 100MHz
CLK
CMD ACT
RDa
tVCVC=4
RDb ^{CASE I)}
RDb ^{CASE II)}
RDb ^{CASE III)}
tCC=10ns
CASE I )
CASE II )
CASE III )
Qb0 Qb1 Qb2 Qb3
(Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 2, CL = 5, BL = 4 ; 83MHz
CLK
CMD ACT
RDa
tVCVC=4
RDb ^{CASE I)}
RDb ^{CASE II)}
RDb ^{CASE III)}
tCC=12ns
CASE I )
CASE II )
CASE III )
Qb0 Qb1 Qb2 Qb3
(Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 4, BL = 4 ; 66MHz
CLK
tVCVC=3
CMD ACT RDa
RDb ^{CASE I)}
RDb ^{CASE II)}
RDb ^{CASE III)}
tCC=15ns
CASE I )
CASE II )
CASE III )
Qb0 Qb1 Qb2 Qb3
Qa0 Qa1 Qb2
Qb1 Qb2 Qb3
(Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data