K3S7V2000M-TC Datasheet, PDF (15/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
Read Cycle III : Clock Suspend @RAS Latency = 2, CAS Latency=5, Burst Length=4
tCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
CKE
tCC
tCL
*Note 1
Internal
CLK
CS
RAS
Latency
tSH
RAS
tSS
CAS
ADDR
tSH
RAa
tSS
CAa
tVCVC= 4 clocks at BL=4
Data
Burst Length=4
Qa0
Qa1
*Note 2
Qa2 Qa3
MR
Row Active Read
Clock Suspend Resume
Note :
1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held & maintained.
: Don't Care