K3S7V2000M-TC Datasheet, PDF (5/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
AC OPERATING TEST CONDITIONS(TA = 0 to 70°C, VDD = 3.3V±0.3V, unless otherwise noted.)
Parameter
Timing Reference Levels of Input/Output Signals
Input Signal Levels
Transition Time (Rise & Fall) of Input Signals
Output Load
Value
1.4V
VIH/VIL=2.4V/0.4V
tr/tf=1ns/1ns
LVTTL
Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi-
tion time is measured between VIL(Max) and VIH(Min).
3.3V
Vtt=1.4V
Output
870Ω
1200Ω
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, IOL=2mA
50pF
Output
Z0=50Ω
50Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETERS
(AC operating conditions unless otherwise noted)
Parameter
CLK Cycle Time
CLK to Valid Output Delay
Data Output Hold Time
CLK High Pulse Width
CLK Low Pulse Width
Row-active to Row-active
Input Setup Time
Input Hold Time
CLK to Output in Low-Z
CLK to Output in High-Z
Transition Time
Valid CAS Enable to Valid
CAS Enable
Symbol
tCC
tSAC
tOH
tCH
tCL
tRC
tSS
tSH
tSLZ
tSHZ
tT
up to 100MHz
Min Max
10
-
6
2
-
3
-
3
-
10
-
2
-
1
-
0
-
-
7
0.1
10
tVCVC
8
-
up to 83MHz
Min Max
12
-
6
2
-
3.5
-
3.5
-
10
-
3
-
1
-
0
-
-
8
0.1
10
8
-
up to 66MHz
Min Max
15
-
-
6
2
-
4
-
4
-
8
-
4
-
2
-
0
-
-
10
0.1
10
7
-
up to 50 Mhz
Min Max
20
-
-
6
2
-
6.5
-
6.5
-
8
-
4
-
2
-
0
-
-
15
0.1
10
7
-
Unit Notes
ns
ns
ns
ns
ns
clks
1
ns
ns
ns
ns
ns
clks
2
Note :
1. These tRC values are for BL=8. For BL=4, tRC=6 clks for up to 100MHz, tRC=6 clks for up to 83MHz, tRC=4 clks for up to 66MHz, tRC=4 clks for up to
50MHz, and tRC=3 clks for up to 33MHz.
RAS latency increase means, a simultaneous tRC increase in the same number of cycles.
( If RAS latency is 3 clks, tRC is 12 clks for BL=8.) Refer to attached technical note for gapless operation.
2. These tVCVC values are for BL=8. For BL=4, tVCVC=4clks for up to 100MHz, tVCVC=4clks for up to 83MHz, tVCVC=3clks for up to 66MHz, tVCVC=3clks for
up to 50MHz, and tVCVC=2clks for up to 33MHz.
Refer to attached technical note for gapless operation.