K3S7V2000M-TC Datasheet, PDF (18/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
Mode Register Set:
@RAS Latency = 2, CAS Latency=5, Burst Length=4
tCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
tCL
tCC
CKE
HIGH
tSH
CS
tSS
RAS
CAS
RAS
Latency
ADDR
Data
Code
RAa
CAa
Data Hi-Z State
Qa0 Qa1 Qa2 Qa3
MR
MRS
Row Active
: Don't Care
Note :
1. After the mode register set is completed, no new commands can be issued for 3CLK cycles.
2. After power up, necessarily mode register set should be completed at least one time and CS or MR must be fixed "H" within
3clock cycles, and when user wants to change mode register set, user must exit from power down mode and start mode reg-
ister set before chip enters normal operation mode.