K3S7V2000M-TC Datasheet, PDF (14/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
Read Cycle II : Consecutive Column Access @RAS Latency = 2, CAS Latency=5, BL = 4
tCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
tCL
tCC
CKE
HIGH
CS
RAS
Latency
tSH
RAS
tSS
tSH
tSS
CAS
ADDR
Data
tSH
RAa
tSS
CAa
CAb
*Note 1
tVCVC=4 clocks at BL=4
Burst Length=4
tOH
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
tSAC
tSHZ
MR
Row Active Read
Read
Note:
When column access is initiated beyond tVCVC,
1. at BL=4, CAa access read is completed, CAb access read begins.
: Don't Care