K3S7V2000M-TC Datasheet, PDF (17/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
Synch. MROM
Power Down & Clock Suspend Cycle :
@RAS Latency = 2, CAS Latency=5, Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSS
CKE
*Note 1
*Note 1
Power Down
Clock Suspend
CLK
(internal)
CS
RAS
CAS
ADDR
Data
*Note 2 ^tSH
NOP RAa
tSS
Data Hi-Z State
CAa
Qa0 Qa1
Qa2
Qa3
MR ^(High)
Power-down
Entry
Row Active Read
Power-down
Exit
Clock Suspend ^{Clock Suspend}
Entry
Exit
Note :
1. From next clock after CKE goes low, clock suspend and power down begins.
2. After power down exit, NOP should be issued and new command can be issued after 1clock.
: Don't Care