K3S7V2000M-TC Datasheet, PDF (27/27 Pages) Samsung semiconductor – 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

K3S7V2000M-TC
6. Read Cycle depending on tVCVC and tRC
@ RL = 1, CL = 4, BL = 4 ; 50MHz (Gapless Operation)
CLK
tVCVC=4
CMD ^{ACT RDa}
RDb
ACT RDc
tCC=20ns
RDd
Synch. MROM
ACT RDe
Read out
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 Qd0 Qd1 Qd2
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4
tCC=20ns
CMD ^{ACT RDa}
RDb
ACT RDc
RDd
ACT RDe
RDf
Read out
Qa0 Qa1 Qa2 Qa3
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4
CMD ^{ACT RDa}
RDb ACT RDc
Qc0 Qc1 Qc2 Qc3
Qe0
: Invalid Data
tCC=20ns
RDd ACT RDe
RDf
Read out
Qa0 Qa1 Qa2
Qc0 Qc1 Qc2
Qe0 Qe1 Qe2
: Invalid Data