H8S2148 Datasheet, PDF (948/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 26 Electrical Characteristics
Condition A Condition B Condition C
Item
20 MHz
16 MHz
10 MHz
Test
Symbol Min Max Min Max Min Max Unit Conditions
TMR Timer output
delay time
t_TMOD
— 50
— 50
— 100 ns Figure
26.18
Timer reset input
t
TMRS
setup time
30 —
30 —
50 —
Figure
26.20
Timer clock input t
TMCS
setup time
30 —
30 —
50 —
Figure
26.19
Timer Single
t_TMCWH
1.5 —
1.5 —
1.5 —
t_cyc
clock edge
pulse _Both
width _edges
t_TMCWL
2.5 —
2.5 —
2.5 —
PWMX Pulse output
delay time
t
PWOD
— 50
— 50
— 100 ns Figure
26.21
SCI
Input Asynchro- t_Scyc
clock nous
cycle _Synchro-
nous
4—
6—
4—
6—
4—
6—
t_cyc Figure
26.22
Input clock pulse t_SCKW
0.4 0.6 0.4 0.6 0.4 0.6
t_Scyc
width
Input clock rise
t_SCKr
time
— 1.5 — 1.5 — 1.5 t_cyc
Input clock fall
t_SCKf
— 1.5 — 1.5 — 1.5
time
Transmit data
t
TXD
delay time
(synchronous)
— 50
— 50
— 100 ns Figure
26.23
Receive data setup t_RXS
time (synchronous)
50 —
50 —
100 —
ns
Receive data hold t_RXH
time (synchronous)
50 —
50 —
100 —
ns
A/D Trigger input setup t_TRGS
conver- time
ter
30 —
30 —
50 —
ns Figure
26.24
WDT RESO output delay t_RESD
time
— 100 — 120 — 200 ns Figure
26.25
RESO output pulse t
132 —
132 —
132 —
t
RESOW
cyc
width
Note: * Only supporting modules that can be used in subclock operation
Rev. 4.00 Sep 27, 2006 page 904 of 1130
REJ09B0327-0400