H8S2148 Datasheet, PDF (756/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Start
*1
Set SWE bit in FLMCR1
Wait (x) µs
*5
n=1
Set EBR1, EBR2
*3
Enable WDT
Set ESU bit in FLMCR2
Wait (y) µs
Set E bit in FLMCR1
Wait (z) ms
Clear E bit in FLMCR1
Wait (α) µs
Clear ESU bit in FLMCR2
Wait (β) µs
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
*5
Start of erase
*5
Halt erase
*5
*5
*5
Set block start address to verify address
n←n+1
H'FF dummy write to verify address
Wait (ε) µs
*5
Increment
address
NG
Read verify data
Verify data = all 1?
OK
Last address of block?
OK
Clear EV bit in FLMCR1
*2
NG
Clear EV bit in FLMCR1
Wait (η) µs
*5
NG
*4
End of
erasing of all erase
blocks?
OK
Clear SWE bit in FLMCR1
Wait (η) µs
*5
*5
NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
Wait (θ) µs
End of erasing
Erase failure
Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
5. See section 26.2.6, Flash Memory Characteristics, for the values of x, y, z, α, β, γ, ε, η, θ, and N.
Figure 23.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev. 4.00 Sep 27, 2006 page 712 of 1130
REJ09B0327-0400