H8S2148 Datasheet, PDF (176/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 5 Interrupt Controller
5.4 Address Breaks
5.4.1 Features
With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate
an address break interrupt, using the ABRKCR and BAR registers. When an address break
interrupt is generated, address break interrupt exception handling is executed.
This function can be used to detect the beginning of execution of a bug location in the program,
and branch to a correction routine.
5.4.2 Block Diagram
A block diagram of the address break function is shown in figure 5.5.
BAR
ABRKCR
Match
signal
Comparator
Control logic
Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.5 Block Diagram of Address Break Function
Rev. 4.00 Sep 27, 2006 page 132 of 1130
REJ09B0327-0400