H8S2148 Datasheet, PDF (23/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Item
B.3 Functions
Page
1025
Revision (See Manual for Details)
EBR1H'FF82 Flash Memory
EBR2H'FF83 Flash Memory
Figure amended
Read/Write description of bits 7 to 2 (Before) ^*2 → (After) 
Bit
EBR1
7
6
5
4
3
2
1
0
—
—
—
—
—
— EB9/—^*2 EB8/—^*2
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
— R/W^*1*2 R/W^*1*2
Bit
7
6
5
4
3
2
1
0
EBR2
EB7
EB6 EB5
EB4 EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W^*1 R/W
R/W
R/W
R/W
R/W
R/W
R/W
1030
ICCR1H'FF88 IIC1
ICCR0H'FFD8 IIC0
Figure amended
I²C bus interface enable
0 I²C bus interface module disabled, with
SCL and SDA signal pins set to port
function
SAR and SARX can be accessed
1 I²C bus interface module enabled for
transfer operations (pins SCL and SDA
are driving the bus)
ICMR and ICDR can be accessed
1059 SYSCRH'FFC4 System
Figure amended
IOS enable
0 The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
1 The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
the address range is from H'(FF)F000 to H'(FF)F7FF.
Rev. 4.00 Sep 27, 2006 page xxiii of xliv