H8S2148 Datasheet, PDF (317/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

8.12.2 Register Configuration
Table 8.25 summarizes the port B registers.
Table 8.25 Port B Registers
Name
Abbreviation R/W
Port B data direction register PBDDR
W
Port B output data register
PBODR
R/W
Port B input data register
PBPIN
R
Notes: 1. Lower 16 bits of the address.
2. PBDDR has the same address as P7PIN.
3. PBPIN has the same address as P8DDR.
Section 8 I/O Ports
Initial Value
H'00
H'00
Undefined
Address^*1
H'FFBE^*2
H'FFBC
H'FFBD^*3
Port B Data Direction Register (PBDDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be
returned.
Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 1, 2 and 3 (EXPE = 1)
When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins
(D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit
is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if the bit is cleared to 0.
Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or
software standby mode.
Rev. 4.00 Sep 27, 2006 page 273 of 1130
REJ09B0327-0400