H8S2148 Datasheet, PDF (681/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

21.3 Operation
Section 21 RAM
21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to
H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed.
Undefined values are read from these bits, and writing is invalid.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Rev. 4.00 Sep 27, 2006 page 637 of 1130
REJ09B0327-0400