H8S2148 Datasheet, PDF (569/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 16 I²C Bus Interface [Option]
SCL
(master output)
SDA
(master output)
Start condition
generation
SDA
(slave output)
[5]
IRIC
1
2
3
4
5
6
7
8
9
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Slave address
R/W [7]
A
IRTR
ICDR
Note: Data write
timing in ICDR
ICDR Writing
prohibited
address + R/W
ICDR Writing
enable
1
2
bit 7 bit 6
Data 1
Data 1
User processing [4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
[6] ICDR write
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 16.7 Example of Master Transmit Mode Operation Timing
(MLS = WAIT = 0)
16.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The receive procedure and operations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
(1) Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
(2) When ICDR is read (dummy data read), reception is started and the receive clock is output,
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC f1ag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
Rev. 4.00 Sep 27, 2006 page 525 of 1130
REJ09B0327-0400