H8S2148 Datasheet, PDF (117/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

2.8 Processing States
Section 2 CPU
2.8.1 Overview
The CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Processing
states
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Sleep mode
Power-down state
CPU operation is stopped
to conserve power.*
Software standby
mode
Hardware standby
mode
Note: * The power-down state also includes a medium-speed mode, module stop mode,
sub-active mode, sub-sleep mode, and watch mode.
Figure 2.14 Processing States
Rev. 4.00 Sep 27, 2006 page 73 of 1130
REJ09B0327-0400