H8S2148 Datasheet, PDF (1064/1177 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Appendix B Internal I/O Registers
BARA—Break Address Register A
BARB—Break Address Register B
BARC—Break Address Register C
Bit
7
6
5
BARA
A23
A22
A21
Initial value
0
0
0
Read/Write R/W
R/W
R/W
H'FEF5
H'FEF6
H'FEF7
4
3
2
A20
A19
A18
0
0
0
R/W R/W R/W
Interrupt Controller
Interrupt Controller
Interrupt Controller
1
0
A17
A16
0
0
R/W R/W
Specifies address (bits 23 to 16) at which address break is to be generated
Bit
7
6
5
4
3
2
1
0
BARB
A15
A14
A13
A12
A11
A10
A9
A8
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Specifies address (bits 15 to 8) at which address break is to be generated
Bit
7
6
5
4
3
2
1
0
BARC
A7
A6
A5
A4
A3
A2
A1
—
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W R/W
R/W
R/W
—
Specifies address (bits 7 to 1) at which address break is to be generated
Rev. 4.00 Sep 27, 2006 page 1020 of 1130
REJ09B0327-0400