RX110_16 Datasheet, PDF (93/108 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS

RX110 Group
5. Electrical Characteristics
5.8 ROM (Flash Memory for Code Storage) Characteristics
Table 5.44 ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time
After 1000 times of N_PEC
Symbol
N_PEC
t_DRP
Min.
1000
20*^2, *³
Typ.
Max.
Unit
Conditions
—
—
Times
—
—
Year T_a = +85°C
Note 1.
Note 2.
Note 3.
Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
This result is obtained from reliability testing.
Table 5.45 ROM (Flash Memory for Code Storage) Characteristics (2)
High-speed operating mode Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V
Temperature range for the programming/erasure operation: T_a = –40 to +105°C
FCLK = 1 MHz
FCLK = 32 MHz
Item
Symbol
Unit
Min.
Typ. Max.
Min.
Typ. Max.
Programming time
4-byte
t_P4
—
103
931
—
52
489
μs
Erasure time
1-Kbyte
t_E1K
—
8.23
267
—
5.48
214
ms
128-Kbyte
t_E128K
—
203
463
—
Blank check time
4-byte
t_BC4
—
—
48
—
20
228
ms
—
15.9
μs
1-Kbyte
Erase operation forcible stop time
t_BC1K
—
—
1.58
—
—
0.127 ms
t_SED
—
—
21.6
—
—
12.8
μs
Start-up area switching setting time
t_SAS
—
12.6
543
—
6.16
432
ms
Access window time
ROM mode transition wait time 1
ROM mode transition wait time 2
t_AWS
t_DIS
t_MS
—
12.6
543
—
6.16
432
ms
2
—
—
2
—
—
μs
5
—
—
5
—
—
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source.
R01DS0202EJ0120 Rev.1.20
Jul 29, 2016
Page 93 of 108