RX110_16 Datasheet, PDF (89/108 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS

RX110 Group
5. Electrical Characteristics
5.6 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.41 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection level Power-on reset (POR)
V_POR
1.35
1.50
1.65
V
Figure 5.49,
Figure 5.50
Voltage detection circuit
(LVD1)*¹
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det1_9}
V_{det1_A}
V_{det1_B}
V_{det1_C}
V_{det1_D}
3.00
2.91
2.81
2.70
2.60
2.50
2.40
1.99
1.90
1.80
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.06
1.96
1.86
3.20
3.09
2.99
2.88
2.76
2.66
2.56
2.13
2.02
1.92
V
Figure 5.51
At falling edge VCC
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Table 5.42 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T_a = –40 to +105°C
Item
Symbol Min. Typ. Max. Unit
Test Conditions
Voltage detection level
Wait time after power-on
reset cancellation
Wait time after voltage
monitoring 1 reset
cancellation
Voltage detection circuit
(LVD2)*¹
At normal startup*³
During fast startup time*⁴
Power-on voltage monitoring
1 reset disabled*³
Power-on voltage monitoring
1 reset enabled*⁴
V_{det2_0}
V_{det2_1}
V_{det2_2}
V_{det2_3}*²
t_POR
t_POR
t_LVD1
2.71
2.43
1.87
1.69
―
―
―
―
2.90
2.60
2.00
1.80
9.1
1.6
568
100
3.09
2.77
2.13
1.91
―
―
―
―
V Figure 5.52
At falling edge VCC
ms Figure 5.50
μs Figure 5.51
Wait time after voltage monitoring 2 reset cancellation
Response delay time
Minimum VCC down time*⁵
t_LVD2
t_det
t_VOFF
―
100
―
―
―
350
350
―
―
μs Figure 5.52
μs Figure 5.49
μs Figure 5.49,
VCC = 1.0 V or above
Power-on reset enable time
t_W(POR)
1
―
―
ms Figure 5.50,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
Td_(E-A)
―
V_LVH
―
―
―
300
μs Figure 5.51, Figure 5.52
70
―
mV Vdet1_4 selected
60
―
Vdet1_5 to 9, LVD2 selected
―
50
―
When selection is from
among Vdet1_A to B.
―
40
―
When selection is from
among Vdet1_C to D.
Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply
voltage (VCC) is selected.
Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 4. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/LVD.
R01DS0202EJ0120 Rev.1.20
Jul 29, 2016
Page 89 of 108