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RX110_16 Datasheet, PDF (73/108 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS
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RX110 Group
5. Electrical Characteristics
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C, C = 30 pF
Item
Symbol
Min.
Max.
Unit Test Conditions
RSPI RSPCK clock cycle Master
Slave
tSPcyc
2
8
4096
4096
tPcyc Figure 5.39
*1
RSPCK clock
high pulse width
Master
tSPCKWH (tSPcyc – tSPCKr –
—
ns
tSPCKf)/2 – 3
Slave
(tSPcyc – tSPCKr –
—
tSPCKf)/2
RSPCK clock
low pulse width
Master
tSPCKWL (tSPcyc – tSPCKr–
—
ns
tSPCKf)/2 – 3
Slave
(tSPcyc – tSPCKr –
—
tSPCKf)/2
RSPCK clock
rise/fall time
Output 2.7 V or above
1.8 V or above
tSPCKr,
—
tSPCKf
—
10
ns
15
Input
—
1
μs
Data input setup
time
Master 2.7 V or above
1.8 V or above
tSU
10
30
—
ns Figure 5.40 to
—
Figure 5.45
Slave
Data input hold
Master RSPCK set to a division
tH
time
ratio other than PCLKB
divided by 2
25 – tPcyc
tPcyc
—
—
ns
RSPCK set to PCLKB
tHF
0
—
divided by 2
SSL setup time
SSL hold time
Data output delay
time
Slave
Master
Slave
Master
Slave
Master 2.7 V or above
1.8 V or above
tH
20 + 2 × tPcyc
—
tLEAD –30 + N*2 × tSPcyc
—
2
—
tLAG –30 + N*3 × tSPcyc
—
2
—
tOD
—
14
—
30
ns
tPcyc
ns
tPcyc
ns
Data output hold
time
Slave 2.7 V or above
1.8 V or above
Master 2.7 V or above
1.8 V or above
—
—
tOH
0
–20
3 × tPcyc + 65
3 × tPcyc +105
—
ns
—
Slave
0
—
Successive
Master
transmission delay Slave
time
tTD
tSPcyc + 2 × tPcyc 8 × tSPcyc + 2 × tPcyc ns
4 × tPcyc
—
MOSI and MISO
rise/fall time
Output 2.7 V or above
1.8 V or above
Input
tDr, tDf
—
—
—
10
ns
20
1
μs
SSL rise/fall time
Output
Input
tSSLr,
—
tSSLf
—
20
ns
1
μs
Slave access time
2.7 V or above
1.8 V or above
tSA
—
—
6
tPcyc Figure 5.44,
7
Figure 5.45
Slave output release time
2.7 V or above
1.8 V or above
tREL
—
—
5
tPcyc
6
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0202EJ0120 Rev.1.20
Jul 29, 2016
Page 73 of 108
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