RX110_16 Datasheet, PDF (3/108 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS

RX110 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
I/O ports
Module/Function
General I/O ports
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2b)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
I²C bus interface (RIIC)
Serial peripheral interface
(RSPI)
12-bit A/D converter (S12ADb)
Temperature sensor (TEMPSA)
CRC calculator (CRC)
Description
64-pin /48-pin /40-pin /36-pin
 I/O: 50/34/28/24
 Input: 2/2/1/1
 Pull-up resistors: 42/28/23/20
 Open-drain outputs: 38/28/23/20
 5-V tolerance: 4/4/4/4
Capable of selecting the input/output function from multiple pins
 (16 bits × 4 channels) × 1 unit
 Time bases for the four 16-bit timer channels can be provided via up to 8 pulse-input/output lines and
three pulse-input lines
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 13 output compare/input capture registers
 Pulse output mode
 Phase counting mode
 Generation of triggers for A/D converter conversion
 (16 bits × 2 channels) × 1 unit
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits × 1 channel
 Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
 Clock source: Sub-clock
 Calendar count mode or binary count mode selectable
 Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
 3 channels (channel 1, 5: SCIe, channel 12: SCIf)
 Serial communications modes: Asynchronous, clock synchronous, and smart card interface
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB first or MSB first transfer
 Average transfer rate clock can be input from MTU2 timers
 Simple I²C
 Simple SPI
 Master/slave mode supported (SCIf only)
 Start frame and information frame are included (SCIf only)
 Start-bit detection in asynchronous mode: Low level or falling edge is selectable (SCIe/SCIf)
 1 channel
 Communications formats:
I²C bus format/SMBus format
 Master mode or slave mode selectable
 Supports fast mode
 1 channel
 Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
 Capable of handling serial transfer as a master or slave
 Data formats
 Choice of LSB first or MSB first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
 Double buffers for both transmission and reception
 1 unit (1 unit × 14 channels)
 12-bit resolution
 Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz
 Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
 Double trigger mode (duplication of A/D conversion data)
 A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), or an external trigger signal
 1 channel
 The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
 CRC code generation for arbitrary amounts of data in 8-bit units
 Select any of three generating polynomials:
X⁸ + X² + X + 1, X¹⁶ + X¹⁵ + X² + 1, or X¹⁶ + X¹² + X⁵ + 1
 Generation of CRC codes for use with LSB first or MSB first communications is selectable.
R01DS0202EJ0120 Rev.1.20
Jul 29, 2016
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