RX110_16 Datasheet, PDF (49/108 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS

RX110 Group
5. Electrical Characteristics
Table 5.7 DC Characteristics (5) (2/2)
Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T_a = –40 to +105°C
Item
Symbol
Typ
*⁴
Max
Unit
Test
Conditions
Supply
current*¹
Low-speed
operating mode
Normal
operating
mode
No peripheral operation*⁷ ICLK = 32.768 kHz I_CC
3.9
—
μA
All peripheral operation:
Normal*^8, *⁹
ICLK = 32.768 kHz
10.4 —
All peripheral operation:
Max.*^8, *⁹
ICLK = 32.768 kHz
— 36
Sleep mode No peripheral operation*⁷ ICLK = 32.768 kHz
2.1 —
All peripheral operation: ICLK = 32.768 kHz
Normal*⁸
5.6 —
Deep sleep
mode
No peripheral operation*⁷ ICLK = 32.768 kHz
All peripheral operation: ICLK = 32.768 kHz
Normal*⁸
1.7 —
3.9 —
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. The clock source is HOCO. FCLK and PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. The clock source is HOCO. FCLK and PCLK are set to the same frequency as
ICLK.
Note 4. Values when VCC = 3.3 V.
Note 5. Clock supply to the peripheral functions is stopped. The clock source is the main oscillation circuit when ICLK = 12 MHz and
HOCO when ICLK = 8 or 1 MHz. FCLK and PCLK are set to divided by 64.
Note 6. Clocks are supplied to the peripheral functions. The clock source is the main oscillation circuit when ICLK = 12 MHz and HOCO
when ICLK = 8 or 1 MHz. FCLK and PCLK are set to the same frequency as ICLK.
Note 7. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to
divided by 64.
Note 8. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the
same frequency as ICLK.
Note 9. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to “transition to the module stop state is
made”.
18
16
T_a = 85/105°C, ICLK = 32 MHz^*2
14
12
T_a = 25°C, ICLK = 32 MHz^*1
10
T_a = 85/105°C, ICLK = 16 MHz^*2
8
T_a = 85/105°C, ICLK = 8 MHz^*2
6
4
T_a = 25°C, ICLK = 16 MHz^*1
2
T_a = 25°C, ICLK = 8 MHz^*1
0
1.5
2.0
2.5
3.0
3.5
4.0
VCC (V)
Note 1. All peripheral operation is normal. Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. Average value of the tested upper-limit samples during product
evaluation.
Figure 5.1 Voltage Dependency in High-Speed Operating Mode (Reference Data)
R01DS0202EJ0120 Rev.1.20
Jul 29, 2016
Page 49 of 108