HD151TS206SS Datasheet, PDF (9/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte5 Control Register
Bit Description
Contents
7
48MHz Output Enable
0 = Disabled, 1 = Enabled
6
Reserved
5
VCH Select 66MHz / 48MHz 0 = 3V66 mode
1 = VCH (48MHz) mode
4
Reserved
3
3V66_3/VCH Output Enable 0 = Disabled, 1 = Enabled
2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte6 Control Register
Bit Description
7
Test Clock Mode
6
Reserved
5
Reserved
4
SRC Frequency Select
3
Reserved
2
Spread Spectrum Mode
1
REF1 Output Enable
0
REF0 Output Enable
Contents
0 = Disabled, 1 = Enabled
0 = 100 MHz, 1 = 200 MHz
0 = Spread OFF
1 = Spread ON
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Byte7 Vendor Identification Register
Bit Description
7
Revision Code Bit3
6
Revision Code Bit2
5
Revision Code Bit1
4
Revision Code Bit0
3
Vendor ID Bit3
2
Vendor ID Bit2
1
Vendor ID Bit1
0
Vendor ID Bit0
Contents
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Type
RW
RW
RW
Default
1
1
0
Note
RW 1
RW 1
RW 1
RW 1
RW 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
1
1
Note
See
B9[7:6]
Type
R
R
R
R
R
R
R
R
Default
0
0
0
1
1
1
1
1
Note
Rev.1.00, Apr.28.2003, page 9 of 34