HD151TS206SS Datasheet, PDF (8/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Table1 CPU Clock Power Management Truth Table
Signal
Pin PWRDWN#
PWRDWN#
Tristate Bit
Byte2[5:3]
Note
CPU[2:0]
1
X
Running
CPU[2:0]
0
0
Driven @ Iref x2
See Note1
CPU[2:0]
0
1
Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA.
Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)
Table2 SRC Clock Power Management Truth Table
Signal
Pin PWRDWN#
PWRDWN#
Tristate Bit
Byte2[7]
Note
SRC
1
X
Running
SRC
0
0
Driven @ Iref x2
See Note1
SRC
0
1
Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA.
Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω), Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)
Byte3 Control Register
Bit Description
7
Reserved
6
Reserved
5
PCI_5 Output enable
4
PCI_4 Output enable
3
PCI_3 Output enable
2
PCI_2 Output enable
1
PCI_1 Output enable
0
PCI_0 Output enable
Contents
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Note
Byte 4 Control Register
Bit Description
7
Reserved
6
48_24MHz Output Enable
5
Reserved
4
Reserved
3
Reserved
2
PCIF_2 Output enable
1
PCIF_1 Output enable
0
PCIF_0 Output enable
Contents
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
1
0
0
0
1
1
1
Note
Rev.1.00, Apr.28.2003, page 8 of 34