HD151TS206SS Datasheet, PDF (12/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte10 Control Register
Bit Description
Contents
Type Default Note
7
SSC Spread Select Bit[2:0] Bit[2:0] =
6
000 = –0.500%, 100 = ±0.250%
001 = –0.750%, 101 = ±0.375%
5
010 = –1.000%, 110 = ±0.500%
011 = –1.500%, 111 = ±0.750%
RW 0
RW 0
RW 0
4
Backup of latch Input FS_4 When SAFE_F# is Enable (B15[5]=1) R
X
at Power ON
PWRDWN#/SAFE_F# pin to “Low”,
3
Backup of latch Input FS_3 ^{and if B23[1]=0, frequency selection is} R
X
at Power ON
changed to these setting and
PWRDWN#/SAFE_F# pin to “High”,
2
Backup of latch Input FS_2 _{frequency selection is changed back to} R
X
at Power ON
the last mode.
1
Backup of latch Input FS_1
at Power ON
R
X
0
Backup of latch Input FS_0
at Power ON
R
X
Byte11 Control Register
Bit Description
Contents
Type Default Note
7
Reserved
RW 0
6
Reserved
RW 0
5
PWRDWN# Enable Control 0 = Enable, 1 = Disable
Bit
RW 0
4
Backup of B9[5] written by When SAFE_F# is Enable (B15[5]=1) R
X
I²C
PWRDWN#/SAFE_F# pin to “Low”,
3
Backup of B9[4] written by
and if B23[1]=1, frequency selection is _R
X
I²C
changed to these setting and
PWRDWN#/SAFE_F# pin to “High”,
2
Backup of B9[3] written by _{frequency selection is changed back to} R
X
I²C
the last mode.
1
Backup of B9[2] written by
I²C
R
X
0
Backup of B9[1] written by
I²C
R
X
Rev.1.00, Apr.28.2003, page 12 of 34