HD151TS206SS Datasheet, PDF (14/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte15 Control Register
Bit Description
Contents
Type Default Note
7
PCI_5 Output Frequency
0 = 33.3 MHz , 1 = 25 MHz
Select Bit
R/W 0
6
48_24MHz Output
Frequency Select Bit
0 = 48 MHz , 1 = 24 MHz
R/W 0
5
SAFE_F# Input mode select 0 = PWRDWN# input mode
R/W 0
Bit
1 = SAFE_F# input mode
Default is PWRDWN# input.
SAFE_F# is active “Low” input.
When SAFE_F# is “Low”, frequency
mode is changed to the predefined
frequency mode.
Predefined frequency mode is selected
by B23[1].
4
Clock Divider Control Bit
0 = Normal mode
R/W 0
Clock dividers are changed by Table 5
selection decided B9[5:1]
1 = Over or Down clocking mode
Clock dividers are changed by B15[3:0]
and B16[7:0].
B15[3:0] and B16[7:0] are able to be
changed at B15[4] = 1.
3
CPU Divider Control Bit3
2
CPU Divider Control Bit2
1
CPU Divider Control Bit1
0
CPU Divider Control Bit0
0001 = 1/1, 0101 = 1/5, 1001 = 1/9
R/W X
0010 = 1/2, 0110 = 1/6, 1010 = 1/10 _{R/W X}
0011 = 1/3, 0111 = 1/7, 1011 = 1/11
0100 = 1/4, 1000 = 1/8
R/W X
R/W X
Byte16 Control Register
Bit Description
7
3V66 / PCI / PCIF Divider
Control Bit3
6
3V66 / PCI / PCIF Divider
Control Bit2
5
3V66 / PCI / PCIF Divider
Control Bit1
4
3V66 / PCI / PCIF Divider
Control Bit0
3
SRC Divider Control Bit3
2
SRC Divider Control Bit2
1
SRC Divider Control Bit1
0
SRC Divider Control Bit0
Contents
3V66 divider ratio =
0010 = 1/2, 0110 = 1/6, 1010 = 1/10
0011 = 1/3, 0111 = 1/4, 1011 = 1/11
0100 = 1/4, 1000 = 1/8, 1100 = 1/12
0101 = 1/5, 1001 = 1/9
PCI / PCIF divider ratio = 3V66 x 1/2
Type Default Note
R/W X
R/W X
R/W X
R/W X
0001 = 1/1, 0101 = 1/5, 1001 = 1/9
R/W X
0010 = 1/2, 0110 = 1/6, 1010 = 1/10 _{R/W X}
0011 = 1/3, 0111 = 1/7, 1011 = 1/11
0100 = 1/4, 1000 = 1/8
R/W X
R/W X
Rev.1.00, Apr.28.2003, page 14 of 34