HD151TS206SS Datasheet, PDF (13/34 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4+ Chipset (Springdale)

HD151TS206SS
I²C Controlled Register Bit Map (cont.)
Byte12 Control Register
Bit
7
6
5
4
3
2
1
0
Note:
Description
Contents
Type Default
Reserved
RW 0
Reserved
Reserved
Reserved
RW 0
RW 0
RW 0
Reserved
RW 0
PLL1 Output (VCO1)
0 = Normal mode
RW 0
Frequency Control Bit
PLL1 M1[6:0] and N1[9:0] are changed
(M1/N1 Divider Control Bit) on Table 5 selection decided by
PLL1 : for
FS4/3/2/A/B or B9[5:1]
SRC/3V66/PCI_PLL
1 = Over or Down clocking mode
PLL1 M1[6:0] and N1[9:0] are changed
by B12[1:0] , B13[7:0] and B14[6:0].
B12[1:0] ,B13[7:0] and B14[6:0] are
able to be changed at B12[2] = 1.
PLL1 N1 Divider Control Bit9 N1[9]
RW 0
PLL1 N1 Divider Control Bit8 N1[8]
RW 0
1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Note
See
Note1
Byte13 Control Register
Bit Description
Contents
Type Default
7
6
5
4
3
2
1
0
Note:
PLL1 N1 Divider Control Bit7 N1[7]
R/W 0
PLL1 N1 Divider Control Bit6 N1[6]
R/W 1
PLL1 N1 Divider Control Bit5 N1[5]
R/W 0
PLL1 N1 Divider Control Bit4 N1[4]
R/W 0
PLL1 N1 Divider Control Bit3 N1[3]
R/W 1
PLL1 N1 Divider Control Bit2 N1[2]
R/W 0
PLL1 N1 Divider Control Bit1 N1[1]
R/W 1
PLL1 N1 Divider Control Bit0 N1[0]
R/W 1
1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Note
See
Note1
Byte14 Control Register
Bit
7
6
5
4
3
2
1
0
Note:
Description
Contents
Type Default
Reserved
R/W 0
PLL1 M1 Divider Control Bit6 M1[6]
R/W 0
PLL1 M1 Divider Control Bit5 M1[5]
R/W 0
PLL1 M1 Divider Control Bit4 M1[4]
R/W 1
PLL1 M1 Divider Control Bit3 M1[3]
R/W 0
PLL1 M1 Divider Control Bit2 M1[2]
R/W 0
PLL1 M1 Divider Control Bit1 M1[1]
R/W 1
PLL1 M1 Divider Control Bit0 M1[0]
R/W 0
1. B12[1:0] ,B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Note
See
Note1
Rev.1.00, Apr.28.2003, page 13 of 34